The present invention relates generally to non-volatile memories and in particular the present invention relates to a flash memory device having a mini array to store operating parameters of the flash memory device.
Memory devices are typically provided as internal storage areas in integrated circuit devices. There are several different types of memory. One type of memory is random access memory (RAM). RAM has traditionally been used as main memory in a computer environment. Most RAM is volatile, which means that it requires periodic refresh of electricity to maintain its contents. Another volatile memories include dynamic random access memory (DRAM) and synchronous DRAM (SDRAM). A SDRAM uses a clock pulse to synchronize the transfer of data signals throughout the memory to increase the speed of the memory.
A flash memory is another type of non-volatile memory. A flash memory has its memory array arranged in array blocks of memory cells. Each block can be independently erased with respect to other blocks in the memory array. Typically the memory cells in each block are arranged in row and column fashion. Yet another type of flash memory is a synchronous flash memory. A synchronous flash memory has erasable array blocks and is driven by a clock. In particular, a synchronous flash memory is designed to interface with typical SDRAM systems.
In many memory devices, including flash memory, it is desirable to have the capacity to store certain parameters relating to the operation of the memory. These operating parameters are read and implemented during operation of the memory device. The operating parameters typically relate to voltage levels, timing settings and address redundancy settings. For example, the operating parameters may include program and erase voltage levels or the lengths of erase and soft program pulses. Typically, the operating parameters are transferred to volatile latches and are read and applied during start up or initialization of the device. In the past, fuse elements were used to store these parameters in the local latches. Typically, the manufacture of the memory would blow the fuses permanently. This, however, is limiting because the operating parameters cannot be modified after production.
A memory device having a non-volatile data storage unit in which the operating parameters can be stored and altered at any time after production, is disclosed in U.S. Pat. No. 5,864,499 and is incorporated herein. As disclosed in U.S. Pat. No. 5,864,499, a volatile memory latch circuit and a non-volatile memory device are used to store operating parameters. In this device, non-volatile memory cells in the non-volatile memory device are used as fuses. A limitation of this fuse circuit is the amount of die space required to fabricate and implement the fuse. For each device you typically need two non-volatile cells, a multiplexer and its own sense amplifier. Another limitation to the fuse circuit is the inability of product and test engineers to gage how well the fuse elements are programmed or erased and forecast data retention time periods.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device having an improved method of storing operating parameters.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory device comprising at least one array block of memory, one or more local latches and a mini array is disclosed. The local latches are used to store one or more operating parameters. The mini array also stores the one or more operating parameters in non-volatile memory cells. The one or more operating parameters are retrieved from the mini array and stored in an associated local latch during initialization of the flash memory device.
In another embodiment, a non-volatile memory device comprises a plurality of erasable blocks of flash memory cells, a control array of flash memory cells to store operating parameters, a plurality of local latches to latch operating parameters and control circuitry to control memory operations of the blocks of flash memory cells and the control array. The control circuit reads the operating parameters in the control array and stores the operating parameters in associated local latches.
In another embodiment, a flash memory device comprises a primary array, a secondary array, a plurality of latches and a state machine. The primary array is made up of non-volatile memory cells used to store data. The memory cells in the primary array are arranged in rows and columns. The secondary array is made up of non-volatile memory cells used to store operating parameters. The memory cells in the secondary array are also arranged in rows and columns. The plurality of local latches are used to latch operating parameters. The state machine is used to control memory operations. During initialization, the state machine reads the operating parameters in the secondary array and stores each operating parameter in an associated local latch.
In another embodiment, a flash memory system comprises a processor to provide external commands, a plurality of memory blocks, a control array to store operating parameters, a plurality of local latches to latch operating parameters and control circuitry. The control circuitry is coupled to control memory operations in the plurality of memory blocks, the control array and the local latches. In addition, the control circuitry is also coupled to receive the external commands from the processor. The control circuitry reads the operating parameters in the control array and stores them in selected local latches during initialization of the flash memory system.
A method of operating a flash memory comprising, reading an operating parameter in a memory cell in a secondary array with a sense amplifier, storing the operating parameter in an associated local latch and implementing the operating parameter during initialization of the flash memory.
Another method of operating a flash memory comprising, starting initialization of the flash memory, addressing a memory cell in a mini array, reading the memory cell in the mini array, storing data read from the memory cell in the mini array to an associated local latch to provide an operating parameter for the flash memory and completing initialization of the flash memory.
A method of setting an operating parameter in a flash memory comprising, applying selective operating parameters to a local latch, implementing the operating parameters in the local latch, monitoring the flash memory for results of the operating parameters and when a desired result is achieved, storing the operating parameter responsible for the desired result in an associated memory cell in a mini array.
A method of testing cell margin of memory cells in a control array that stores operating parameters comprising, varying the control gate voltage of the memory cells in the control array on successive read operations, reading the memory cells after each time the control gate has been varied and determining each cell margin.
A method of testing cell margin of memory cells in a control array that stores operating parameters comprising, varying the sense amplifier trigger timing on successive read operations, reading the memory cells after each time the trigger timing has been varied and determining each cell margin.